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general description the MAX14826 transceiver is suitable for io-link ? devices and 24v binary sensors. all specified io-link data rates are supported. in io-link applications, the transceiver acts as the physical layer interface to a micro - controller running the data-link layer protocol. additional 24v digital inputs and outputs are provided. two internal linear regulators generate common sensor and actuator power requirements: 5v and 3.3v. on-board c/q and do drivers are independently-config - urable for push-pull, high-side (pnp), or low-side (npn) operation. the device detects the io-link c/q wake-up condition and generates a wake-up signal on the active- low wu / thsd output. the MAX14826 includes a selectable parallel or spi interface for configuration and monitoring of the drivers. extensive alarm conditions are detected and communi - cated through the interrupt outputs and the spi interface. the device features reverse-polarity, short-circuit, and thermal protection. all power lines are monitored for undervoltage conditions. the c/q and do drivers are specified for sinking/sourcing 200ma. the MAX14826 is available in a 4mm x 4mm, 24-pin tqfn package, and is specified over the extended -40c to +105c temperature range. applications io-link sensors io-link actuators industrial sensors and actuators benefts and features io-link specification v.1.0 and v.1.1 physical layer compliant high configurability and integration reduce skus ? push-pull, high-side, or low-side outputs ? supports com1, com2, and com3 data rates ? spi or pin-driven control and monitoring ? 2.5v to 5v logic interface levels ? c/q and do drivers can be connected in parallel ? auxiliary 24v, 200ma digital output (do) ? auxiliary 24v digital input (di) ? integrated 5v and 3.3v linear regulators ? driver currents specifed for 200ma, 100ma and 50ma ? 1f c/q and do load drive capability integrated protection enables robust solutions ? extensive fault-monitoring and reporting ? reverse-polarity and short-circuit protection on all 24v inputs/outputs ? reverse-polarity protected 24v supply output ? -40c to +105c operating temperature range backwards pin-and software-compatible to max14821 space-saving 4mm x 4mm tqfn package ordering information appears at end of data sheet. io-link is a registered trademark of profibus user organization (pno). 19-7129; rev 0; 9/14 max 14826 gnd c / q do v cc ldoin v 5 l + l - 1 4 3 2 di v p 1 f 0 . 1 f 1 f 0 . 8 ? microcontroller v cc 3 . 3 v 5 v v l ldo 33 dodis gpio 2 uv 10 k ? spi rx rx irq wu / thsd tx tx rts txen gpio 1 lo gnd 10 ? 1 f spi / par typical application circuit MAX14826 io-link device transceiver
3 . 3 v ldo 5 v ldo driver filter ldo 33 v p ldoin v 5 gnd c / q v cc txen tx rx wake - up detect wu protection do lo driver v l status & configuration spi / par uv wu / thsd irq / cqoc sdo / dooc sclk / cqpp sdi / dopp cs / pnp uv monitor v l filter di li protection v drv v drv dodis max 14826 maxim integrated 2 functional diagram MAX14826 io-link device transceiver www.maximintegrated.com
(all voltages referenced to gnd, unless otherwise noted.) v cc ......................................................................... -40v to +40v v p (i vp < 50ma) ..... the higher of -0.3v and (v cc - 1v) to +40v ldoin .................................................................... -0.3v to +40v v 5 .................... -0.3v to the lesser of (v ldoin + 0.3v) and +6v ldo33 ..................... -0.3v to the lesser of (v 5 + 0.3v) and +6v v l ............................................................................ -0.3v to +6v di ........................................................................... -40v to +40v c/q, do ...................... min: the higher of -40v and (v cc - 40v) max: the lesser of +40v and (v cc + 40v) logic inputs tx, txen, lo, cs /pnp, sdi/dopp, sclk/cqpp ............................................ -0.3v to (v l + 0.3v) logic outputs rx, wu / thsd , li, sdo/ dooc , irq / cqoc ............................................... -0.3v to (v l + 0.3v) uv ........................................................................ -0.3v to +6v continuous current into any logic pin ........................... q 50ma continuous power dissipation tqfn (derate 27.8mw/c above +70c) .................. 2222mw operating temperature range ......................... -40c to +105c maximum junction temperature ..................................... +150c storage temperature range ............................ -65c to +150c lead temperature (soldering, 10s) ................................. +300c soldering temperature (reflow) ....................................... +260c tqfn junction-to-ambient thermal resistance ( ja ) ........... 36c/w junction-to-case thermal resistance ( jc ) ................. 3c/w (note 1) dc electrical characteristics (v cc = 18v to 36v, v l = 2.3v to 5.5v, v gnd = 0v; all logic inputs at v l or gnd; t a = -40c to +105c, unless otherwise noted. typical values are at v cc = 24v, v l = 3.3v, and t a = +25c, unless otherwise noted.) (note 2) parameter symbol conditions min typ max units v cc supply voltage v cc for driver operation 9 36 v v cc supply current i cc v cc = 24v, c/q as input, no load on v 5 or ldo33, ldoin not connected to v p , v ldoin = 24v 1.2 2.5 ma v cc undervoltage lockout threshold v ccuvlo v cc falling 6 7.4 8.4 v v cc undervoltage lockout threshold hysteresis v ccuvlo_hyst 200 mv v 5 supply current i 5_in ldoin shorted to v 5 , external 5v applied to v 5 , no switching, ldo33 disabled 3 ma v 5 undervoltage lockout threshold v 5uvlo v 5 falling 2.4 v v l logic-level supply voltage v l 2.3 5.5 v v l logic-level supply current i l all logic inputs at v l 5 a all logic inputs at gnd 100 a v l undervoltage threshold v luvlo v l falling 0.65 0.95 1.30 v maxim integrated 3 note 1: package thermal resistances were obtained using the method described in jedec specification jesd51-7, using a four-layer board. for detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial . absolute maximum ratings stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to ab solute maximum rating conditions for extended periods may affect device reliability. package thermal characteristics MAX14826 io-link device transceiver www.maximintegrated.com
dc electrical characteristics (continued) (v cc = 18v to 36v, v l = 2.3v to 5.5v, v gnd = 0v; all logic inputs at v l or gnd; t a = -40c to +105c, unless otherwise noted. typical values are at v cc = 24v, v l = 3.3v, and t a = +25c, unless otherwise noted.) (note 2) parameter conditions min typ max units 5v ldo (v 5 ) ldoin input voltage range v ldoin 7 36 v ldoin supply current i ldoin v ldoin = 24v, c/q is confgured as an input, no load on v 5 or ldo33 2.5 5 ma v 5 output voltage range v 5 no load on v 5 , 7v v ldoin 36v 4.75 5.00 5.25 v power supply rejection ratio v 5psrr f ldoin = 100hz 60 88 db v 5 load regulation 1ma < i load < 10ma, v ldoin = 7v, 0.1f bypass capacitor on v 5 0.8 % 1ma < i load < 30ma, v ldoin = 7v, 0.1f bypass capacitor on v 5 , 10?C1f compensation network added to v 5 0.8 3.3v ldo (ldo33) ldo33 output voltage v ldo33 no load on ldo33 3.1 3.3 3.5 v ldo33 undervoltage lockout threshold v ldo33uvlo v ldo33 falling 2.4 v ldo33 load regulation 1ma < i load < 20ma, v ldoin = 7v 0.25 % 24v interface c/q driver output voltage high v oh_c/q c/q high-side enabled, 9v v cc 36v i c/q = -200ma v cc C 1.9 v cc C 1.4 v i c/q = -100ma v cc C 1.4 v cc C 1 i c/q = -50ma v cc C 1.1 v cc C 0.83 c/q driver output voltage low v ol_c/q c/q low-side enabled, 9v v cc 36v i c/q = +200ma 1.55 2 v i c/q = +100ma 1.2 1.7 i c/q = +50ma 0.98 1.3 c/q driver source current limit i oh_c/q c/q high-side enabled, v c/q < (v cc - 5v), 9v v cc 36v +280 +350 +420 ma c/q driver sink current limit i ol_c/q c/q low-side enabled, v c/q > 5v, 9v v cc 36v -423 -350 -280 ma do driver output voltage high v oh_do do high-side enabled, 9v v cc 36v i do = -200ma v cc C 2.1 v cc C 1.5 v i do = -100ma v cc C 1.45 1.1 i do = -50ma v cc C 1.15 0.87 maxim integrated 4 MAX14826 io-link device transceiver www.maximintegrated.com
dc electrical characteristics (continued) (v cc = 18v to 36v, v l = 2.3v to 5.5v, v gnd = 0v; all logic inputs at v l or gnd; t a = -40c to +105c, unless otherwise noted. typical values are at v cc = 24v, v l = 3.3v, and t a = +25c, unless otherwise noted.) (note 2) parameter conditions min typ max units do driver output voltage low v ol_do do low-side enabled, 9v v cc 36v i do = +200ma 1.6 2.3 v i do = +100ma 1.24 1.75 i do = +50ma 1.04 1.4 do source current limit i oh_do do high-side enabled, v do < (v cc - 5v) -470 -340 -263 ma do sink current limit i ol_do do low-side enabled, v do > 5v 270 360 480 ma c/q, di input voltage range v in for valid rx, li -1.0 v cc + 1.0 v c/q input threshold high v ih_c/q c/q driver disabled 10.5 13 v c/q input threshold low v il_c/q c/q driver disabled 8.0 11.5 v c/q input hysteresis v hys_c/q c/q driver disabled 1.0 1.6 v di input threshold high v ih_di 6.8 8 v di input threshold low v il_di 5.2 6.4 v di input hysteresis v hys_di 1 1.6 v c/q weak pulldown current i pdc/q c/q driver disabled, v c/q = (v cc - 1v) 48 100 a do leakage current i pddo do driver disabled, v cc = 36v, v do = (v cc - 1v) -1 +1 a di weak pulldown current i pddi v cc = 36v, v di = (v cc - 1v) 102 a c/q input capacitance c c/q c/q driver disabled 40 pf do input capacitance c do do driver disabled 40 pf di input capacitance c di 20 pf logic inputs (tx, txen, lo, cs /pnp, sdi/dopp, sclk/cqpp, spi/ par, dodis) logic-input voltage low v il 0.3 x v l v logic-input voltage high v ih 0.7 x v l v logic-input leakage current high i leak_h logic input = v l -2 +2 a logic-input leakage current low i leak_l tx, txen, lo, cs /pnp, sdi/dopp, sclk/cqpp, logic input = gnd -2 +2 a spi/ par pull-up resistance r puspi 100 k? logic-input capacitance c in 5 pf maxim integrated 5 MAX14826 io-link device transceiver www.maximintegrated.com
dc electrical characteristics (continued) (v cc = 18v to 36v, v l = 2.3v to 5.5v, v gnd = 0v; all logic inputs at v l or gnd; t a = -40c to +105c, unless otherwise noted. typical values are at v cc = 24v, v l = 3.3v, and t a = +25c, unless otherwise noted.) (note 2) parameter symbol conditions min typ max units logic outputs (rx, wu / thsd , li, uv, sdo/ dooc , irq / cqoc ) logic-output voltage low v ol i out = -5ma 0.4 v logic-output voltage high v ohrx , v ohwu , v ohli , v ohsdo, v ohirq , i out = 5ma (note 3) v l - 0.6 v sdo/ dooc leakage current i lk_sdo sdo/ dooc disabled, sdo/ dooc = gnd or v l -2 +2 a sdo/ dooc output voltage high v sdo_dooc spi/ par = gnd; i out = 5ma v l - 0.6v v thermal shutdown thermal warning threshold die temperature rising, otemp bit is set +127 c thermal warning threshold hysteresis die temperature falling, otemp bit is cleared +23 c thermal-shutdown threshold die temperature rising +165 c thermal-shutdown hysteresis 20 c maxim integrated 6 MAX14826 io-link device transceiver www.maximintegrated.com
ac electrical characteristics (v cc = 18v to 36v, v l = 2.3v to 5.5v, v gnd = 0v; all logic inputs at v l or gnd; t a = -40c to +105c, unless otherwise noted. typical values are at v cc = 24v, v l = 3.3v, and t a = +25c, unless otherwise noted.) (note 2) parameter symbol conditions min typ max units driver (c/q, do) driver low-to-high propagation delay t pdlh push-pull or high-side (pnp) confguration, figure 1 0.5 2 s driver high-to-low propagation delay t pdhl push-pull or low-side (npn) confguration, figure 1 0.5 2 s driver skew t skew |t pdlh - t pdhl | 0.1 2 s driver rise time t rise push-pull or high-side (pnp) confguration, figure 1 0.4 1 s driver fall time t fall push-pull or low-side (npn) confguration, figure 1 0.4 1 s driver enable time high t enh push-pull or high-side (pnp) confguration, figure 3 0.3 1 s driver enable time low t enl push-pull or low-side (npn) confguration, figure 2 0.3 1 s driver disable time high t dish push-pull or high-side (pnp) confguration, figure 2 (note 4) 1.6 3 s driver disable time low t disl push-pull or low-side (npn) confguration, figure 3 (note 4) 0.1 3 s receiver (c/q, di) (figure 4) receiver low-to-high propagation delay t prlh rxfilter = 1 (note 5), figure 4 0.2 2 s rxfilter = 0, figure 4 0.4 2 receiver high-to-low propagation delay t prhl rxfilter = 1 (note 5), figure 4 0.3 2 s rxfilter = 0, figure 4 0.5 2 wake-up detection (figure 5) wake-up input minimum pulse width t wumin 30 40 50 s wake-up input maximum pulse width t wumax 120 140 160 s wu / thsd output low time t wul valid wake-up condition on c/q 120 200 260 s short-circuit detection short-circuit blanking time t shblk 0.17 0.214 0.252 ms short-circuit auto-retry time t shar 11 12.9 14.6 ms maxim integrated 7 MAX14826 io-link device transceiver www.maximintegrated.com
ac electrical characteristics (continued) (v cc = 18v to 36v, v l = 2.3v to 5.5v, v gnd = 0v; all logic inputs at v l or gnd; t a = -40c to +105c, unless otherwise noted. typical values are at v cc = 24v, v l = 3.3v, and t a = +25c, unless otherwise noted.) (note 2) note 2: all devices are 100% production tested at t a = +25c. limits over the operating temperature range are guaranteed by design. note 3: uv is an open-drain output. connect uv to a voltage less than 5.5v through an external pullup resistor. note 4: disable time measurements are load-dependent. note 5: rxfilter is on by default in parallel mode (spi/ par is low). parameter symbol conditions min typ max units spi timing ( cs /pnp, sclk/cqpp, sdi/dopp, sdo/ dooc ) (figure 6) sclk/cqpp clock period t ch+cl 83.3 ns sclk/cqpp pulse-width high t ch 41.65 ns sclk/cqpp pulse-width low t cl 41.65 ns cs /pnp fall to sclk/cqpp rise time t css 20 ns sclk/cqpp rise to cs /pnp rise hold time t csh 20 ns sdi/dopp hold time t dh 10 ns sdi/dopp setup time t ds 10 ns output data propagation delay t do 36 ns sdo/ dooc rise and fall times t ft 20 ns minimum cs /pnp pulse t csw 76.8 ns maxim integrated 8 MAX14826 io-link device transceiver www.maximintegrated.com
figure 1. c/q and lo driver propagation delays and rise/fall times figure 2. c/q driver enable low and disable high timing with external pullup resistor tx c/q or do txen tx or lo c/q or do t pdhl t fall t rise t pdlh 90% v l v l v cc 0v 0v 0v 50% 50% 10% 3.3nf 5k? txen gnd lo MAX14826 v l tx c/q v cc txen c/q t enl t dish v l v cc 0v 0v 90% 10% 3.3nf 5k? txen gnd MAX14826 maxim integrated 9 MAX14826 io-link device transceiver www.maximintegrated.com
figure 3. c/q driver enable high and disable low timing figure 4. c/q and di receiver propagation delays c/q 3.3nf 5k? txen gnd tx txen c/q t enh t disl v l v cc 0v 0v 10% 90% MAX14826 rx or li c/q or di rx or li t prlh t prhl v cc v l 0v 0v 50% 50% 15pf gnd txen MAX14826 c/q or di maxim integrated 10 MAX14826 io-link device transceiver www.maximintegrated.com
figure 5. wake-up detection timing figure 6. spi timing diagram txen tx note: the MAX14826 recognizes a wake-up pulse when c/q is shorted from high-to-low or from low-to-high for t wumin < t wu < t wumax . c/q t wumin < t wu < t wumax t wul < t wumin no wake-up tx txen gnd c/q wu/thsd wu/thsd MAX14826 t csh t cl t css t ch t csh cs/pnp sclk/cqpp sdi/dopp sdo/dooc t ds t dh t do maxim integrated MAX14826 io-link device transceiver www.maximintegrated.com
(v cc = 24v, ldoin = v p , v l = ldo33, c/q and do in push-pull confguration, t a = +25c, unless otherwise noted.) 0 1 2 3 4 5 6 7 0 50 100 150 200 250 300 350 400 v oh_c/q (v) load current (ma) c/q driver output high vs. load current toc01 t a = - 40c t a = +25 c t a = +105 c 0 1 2 3 4 5 6 7 0 50 100 150 200 250 300 350 400 v oh_do (v) load current (ma) do driver output high vs. load current toc03 t a = - 40c t a = +25 c t a = +105 c 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 -45 -30 -15 0 15 30 45 60 75 90 105 t pdhl (s) temperature ( c) c/q driver propagation delay vs. temperature toc05 tx to c/q c l = 3.3nf on c/q 0 1 2 3 4 5 6 7 0 50 100 150 200 250 300 350 400 v ol_c/q (v) sink current (ma) c/q driver output low vs. sink current toc02 t a = - 40c t a = +25 c t a = +105 c 0 1 2 3 4 5 6 7 0 50 100 150 200 250 300 350 400 v ol_do (v) sink current (ma) do driver output low vs. sink current toc04 t a = - 40c t a = +25 c t a = +105 c c/q driver output switching toc06 2s/div v tx v c/q 0v 0v 2v/div 5v/div maxim integrated 12 typical operating characteristics MAX14826 io-link device transceiver www.maximintegrated.com
(v cc = 24v, ldoin = v p , v l = ldo33, c/q and do in push-pull confguration, t a = +25c, unless otherwise noted.) c / q s h o r t - c i r c u i t p r o t e c t i o n ( h i g h - t o - l o w , s p i m o d e ) 1 0 v / d i v 2 v / d i v t oc 09 4 0 s/ d i v i s h o r t o u t o f c / q v i r q 0 v 0 v v c / q 2 0 0 m a / d i v 0 m a s p i m o d e tx = v l t s h o r t = 2 5 0 s 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 -45 -30 -15 0 15 30 45 60 75 90 105 t rphl (s) temperature ( c) receiver propagation delay vs. temperature toc07 t rplh , rxfilter = 1 c/q to rx t rphl , rxfilter = 1 t rplh , rxfilter = 0 t rphl , rxfilter = 0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 9 12 15 18 21 24 27 30 33 36 i ldoin (ma) v ldoin (v) ldoin supply current vs. ldoin voltage toc11 t a = - 40c t a = +25 c t a = +105 c wake - up detection 10v/div 2v/div toc08 40s/div v c/q v wu 0v 0v spi mode c / q s h o r t - c i r c u i t p r o t e c t i o n ( l o w - t o - h i g h , s p i m o d e ) 1 0 v / d i v 2 v / d i v t oc 10 4 0 s/ d i v i s o u r c e v i r q 0 v 0 v v c / q 2 0 0 m a / d i v 0 m a s p i m o d e tx = v l t s h o r t = 2 5 0 s c / q s h o r t - c i r c u i t p r o t e c t i o n ( p i n c o n t r o l m o d e ) 1 0 v / d i v 2 v / d i v t oc 12 4 0 m s/ d i v i s o u r c e v c q o c 0 v 0 v v c / q 2 0 0 ma / d i v 0 m a p i n c o n t r o l m o d e tx = g n d t s h o r t = 2 0 m s maxim integrated 13 typical operating characteristics (continued) MAX14826 io-link device transceiver www.maximintegrated.com
(v cc = 24v, ldoin = v p , v l = ldo33, c/q and do in push-pull confguration, t a = +25c, unless otherwise noted.) d o s h o r t - c i r c u i t p r o t e c t i o n ( p i n c o n t r o l m o d e ) 1 0 v / d i v 2 v / d i v t oc 13 4 0 m s/ d i v i s o u r c e v d o o c 0 v 0 v v d o 2 0 0 ma / d i v 0 m a p i n c o n t r o l m o d e l o = g n d t s h o r t = 2 0 m s 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 9 12 15 18 21 24 27 30 33 36 i cc (ma) v cc voltage (v) v cc supply current vs. v cc voltage toc17 t a = - 40c t a = +25 c t a = +105 c no switching on c/q or do v ldoin = 7v -1.5 -1.4 -1.3 -1.2 -1.1 -1.0 -0.9 -0.8 -0.7 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0.0 0 10 20 30 40 50 % voltage change load current (ma) v5 load regulation toc14 t a = - 40c t a = +25 c t a = +105 c -2.0 -1.8 -1.6 -1.4 -1.2 -1.0 -0.8 -0.6 -0.4 -0.2 0.0 0 10 20 30 40 50 % voltage change load current (ma) ldo33 load regulation toc15 t a = - 40c t a = +25 c t a = +105 c 0 2 4 6 8 10 12 14 1 10 100 1000 i cc (ma) c/q data rate (kbps) v cc supply current vs. c/q data rate no load on c/q do is disabled ldoin = v 5 = 5v txen = v l toc16 v cc = 24v v cc = 30v v cc = 36v maxim integrated 14 typical operating characteristics (continued) MAX14826 io-link device transceiver www.maximintegrated.com
pin name function 1 ldoin 5v linear regulator input. bypass ldoin to gnd with a 1f ceramic capacitor. ldoin can be powered from v p or from an external source in the 7v to 36v range. if using v p to power the ldo, connect ldoin to v p through a 10 w resistor. 2 v 5 5v power-supply input and 5v linear regulator output. bypass v 5 to gnd with a 0.1f ceramic capacitor for 10ma load capability. add the recommended compensation network to increase the source capability to 30ma. see the 5v and 3.3v linear regulators section for more information. 3 ldo33 3.3v linear regulator output. bypass ldo33 to gnd with a 1f ceramic capacitor. 4 irq / cqoc interrupt request output c/q overcurrent indicator. in spi mode, irq / cqoc is a standard active-low interrupt request output activated by the bits in the status register. in parallel mode, irq / cqoc pulses low when an overcurrent condition occurs on c/q. irq / cqoc is a push-pull output referenced to v l . 5 sclk/cqpp spi clock input c/q mode select input. in spi mode, sclk/cqpp is the spi clock input. in parallel mode, sclk/cqpp sets the confguration of the c/q driver. 6 cs /pnp active-low spi chip-select input c/q and do mode select input. in spi mode, cs /pnp is the spi chip- select input.in parallel mode, cs /pnp set the confguration for the c/q and do drivers. 7 sdo/ dooc spi serial-data output/do overcurrent indicator. in spi mode, sdo/ dooc the spi serial-data output. in parallel mode, sdo/ dooc pulses low when an overcurrent condition occurs on do. 8 sdi/dopp spi serial-data input/ do mode select input. in spi mode, sdi/dopp is the spi serial data input. in parallel mode, sdi/dopp sets the confguration of the do driver. 9 v l logic-level supply input. v l defnes the logic levels on all the logic inputs and outputs. bypass v l to gnd with a 0.1f ceramic capacitor. v 5 irq/cqoc sclk/cqpp cs/pnp ldoin li wu/thsd rx uv txen do v cc v p spi/par v l sdi/dopp sdo/dooc ldo33 lo c/q dodis gnd tx di tqfn 4mm x 4mm top view + 13 14 15 16 17 18 12 11 10 9 8 7 19 20 21 22 23 24 6 5 4 3 2 1 MAX14826 *ep *exposed pad. connect to gnd. maxim integrated 15 pin confguration pin description MAX14826 io-link device transceiver www.maximintegrated.com
pin name function 10 spi/ par spi-mode/parallel-mode select input. drive spi/ par high to enable spi functionality. drive spi/ par low to enable parallel-mode operation. 11 dodis do disable input. drive dodis low to enable the do output. drive dodis high to disable the do output. do is high-impedance when dodis is high. 12 tx transmit communication input. the logic on the c/q output is the inverse logic level of the signals on the tx input. 13 txen transmitter enable. drive txen high to enable the c/q transmitter. txen is referenced to v l . 14 rx receiver output. rx is the inverse logic level of c/q. rx is always high when the rxdis bit in the cqconfg register is set to 1. 15 wu / thsd wake-up output/active-low thermal-shutdown indicator. in spi mode, wu / thsd is the wake-up output. in this mode, wu / thsd pulses low for 190s (typ) when a valid wake-up pulse is detected on the c/q line. in parallel mode, wu / thsd is the thermal-shutdown indicator and asserts low during thermal shutdown. wu / thsd is a push-pull output referenced to v l . 16 lo logic input of the do output. lo is the logic input that drives do. lo is referenced to v l . 17 li logic output of the 24v di logic input. li is the inverse logic of di. li is referenced to v l . 18 uv open-drain undervoltage indicator output. in case of an undervoltage, the uv open-drain transistor is off. 19 di 24v logic-level digital input 20 gnd ground 21 c/q sio/io-link data input/output. drive txen high to enable the c/q driver. the logic on the c/q output is the inverse logic level of the signals on the tx input. rx is the logic inverse of c/q. the c/q driver output level can be set by the tx input or programmed by the q bit. the level on c/q can be read by the rx ouput or the q lvl bit. 22 do 24v logic-level digital output. do is the inverse logic level of the lo input and can be digitally-controlled through the dioconfg register. 23 v cc power-supply input. bypass v cc to gnd with a 1f ceramic capacitor. 24 v p protected 24v supply output. v p is one diode drop below v cc . v p is reverse-polarity-protected and can be used as a 24v protected supply to the sensor or actuator electronics. ep exposed pad. connect ep to gnd. maxim integrated 16 pin description (continued) MAX14826 io-link device transceiver www.maximintegrated.com
detailed description the MAX14826 is a sensor/actuator transceiver designed for io-link ? device applications supporting all the speci - fied io-link data rates. in io-link applications, the devices act as the physical layer interface to a microcontroller run - ning the data-link layer protocol. the device contains an additional 24v digital input and an additional 24v digital output. two internal linear regulators generate common sensor and actuator power requirements: 5v and 3.3v. the device detects io-link wake-up conditions on the c/q line and generates a wake-up signal on the wu / thsd output. the c/q and do drivers are independently- configurable to any one of three driver output types: push- pull, high-side (pnp), or low-side (npn). this device is configured and monitored through a pin- selectable parallel or spi ? interface. extensive alarms are available through spi. 24v interface the device features an io-transceiver interface capable of operating with voltages up to 36v. this is the 24v interface and includes the c/q input/output, the logic-level digital output (do), and the logic-level digital input (di). confgurable drivers the device features selectable push-pull, high-side (pnp), or low-side (npn) switching drivers at c/q and do. parallel mode in parallel mode, the c/q and do drivers are indepen - dently-configurable using the cqpp/sclk, dopp/sdi, and pnp/ cs inputs. set cqpp/sclk high to select push- pull operation on the c/q driver. set dopp/sdi high to select the push-pull operation on the do driver. the pnp/ cs input selects npn or pnp operation for driv - ers configured for open-drain operation. set pnp/ cs high for pnp operation. set pnp/ cs low for npn operation. see table 1. spi mode in spi mode, write to the cqconfig and dioconfig regis - ters to configure the c/q and do drivers. set the c/q_n/p and c/q_pp bits in the cqconfig reg - ister to select the driver mode for the c/q driver. when configured as a push-pull output, c/q switches between vp and ground. set the c/q_pp bit to 1 to select push- pull operation at c/q. set the c/q_pp bit to 0 to configure the c/q output for open-drain operation. the c/q_n/p bit selects npn or pnp operation when c/q is configured as an open-drain output. set the don/p and dopp bits in the dioconfig regis - ter to select the driver mode for the do output. when configured as a push-pull output, do switches between v cc and ground. set the dopp bit to 1 for push-pull oper - ation. the don/p bit selects npn or pnp operation when do is configured as an open-drain output. set the dopp bit to 0 to select high-side or low-side operation at do. c/q driver and receiver the c/q driver can be enabled/disabled in either parallel- input mode or spi mode. the devices c/q driver is specified for 200ma to drive large capacitive loads of up to 1f and dynamic imped - ances like incandescent lamps. the maximum load cur - rent for c/q is limited to 480ma. the c/q receiver is always on. in spi mode, the rx out - put through the rxdis bit in the cqconfig register. set the rxdis bit to 1 to set the rx output high. set the rxdis bit to 0 for normal receive operation. the c/q receiver has an analog lowpass filter to reduce high-frequency noise present on the line. c/q fault detection the device registers a c/qfault condition under either of two conditions: 1) when it detects a short-circuit for longer than 214s (typ). a short condition exists when the c/q drivers load current exceeds the 350ma (typ) current limit. 2) when it detects a voltage level error at the c/q output. a voltage level error occurs when the c/q driver is configured for open-drain operation (npn or pnp), the driver is turned off, and the c/q voltage is not pulled to exceed the c/q receivers threshold levels (< 8v or > 13v) by the external supply. when a c/qfault error occurs, the c/qfault and c/qfaultint bits are set, irq / cqoc asserts, and the driver is turned off after the start of the fault condition. io-link is a registered trademark of profibus user organization (pno). spi is a trademark of motorola, inc. table 1. parallel mode select truth table cqpp/sclk dopp/sdi pnp/cs c/q mode do mode low low low npn npn low low high pnp pnp high low low push-pull npn high low high push-pull pnp low high low npn push-pull low high high pnp push-pull high high x push-pull push-pull x = dont care maxim integrated 17 MAX14826 io-link device transceiver www.maximintegrated.com
when a short-circuit event occurs on c/q, the driver enters autoretry mode. in autoretry mode, the device periodically checks whether the short is still present and attempts to correct the driver output. autoretry attempts last for 214s (typ) and occur every 12.9ms (typ). do fault detection the device registers a dofault event when a short-circuit is present at the do output for 214s (typ). a short condition exists when the load current on the do driver exceeds the 300ma (typ) do current limit. when a short-circuit condition is detected, the do driver enters autoretry mode. in autore - try mode the device periodically checks whether the error is still present. autoretry attempts last for 214s (typ) and occur every 12.9ms (typ). when a dofault error is detect - ed, sdo/dooc asserts (parallel mode) or the dofault and dofaultint bits are set, irq / cqoc asserts. the driver is turned off 214s (typ) after the start of the do faults. reverse-polarity protection the device is protected against reverse-polarity connec - tions on v cc , c/q, do, di, and gnd. any combination of these pins can be connected to dc voltages up to 40v (max). a short to 40v results in a current flow of less than 500a. ensure that the maximum voltage between any of these pins does not exceed 40v. 5v and 3.3v linear regulators the MAX14826 includes two internal regulators to gener - ate 5v (v 5 ) and 3.3v (ldo33). v 5 is specified for a total of 10ma load current, including the load from ldo33, when bypassed with a 0.1f capacitor to ground. add the compensation network shown in figure 7 to draw up to 30ma of total external load current from v 5 . ldo33 is specified up to 20ma. the input of v 5 (ldoin) can be powered from v p , the protected 24v supply output, or by another voltage in the 7v to 36v range. if the external circuits powered by the linear regulators require an input bypass capacitance greater than 100nf for 5v, or 1f for 3.3v, a compensation network must be added on the ldo output. in this situation, connect a capacitor equal to the value required by the external cir - cuit to the ldo output and a 10? series resistor between the output and its load (see figure 8 ). the capacitors (c5 and c33) in the figure represent the capacitance required by the external circuits. for simplicity, figure 8 does not show the required protection diodes. the 5v ldo can be disabled by connecting ldoin to v 5 . when the internal 5v ldo is not used, however, v 5 becomes the supply input for the internal analog and digi - tal functions and must be supplied externally for normal operation. apply an external voltage of 4.75v to 5.25v to v 5 when the ldo is disabled. figure 7. v 5 compensation network figure 8. larger bypass capacitance for powering external circuits MAX14826 10? 0.1 f 1 f 1 f v 5 v l 5v ldo33 3.3v max 14826 gnd v cc ldoin v 5 l + l - v p 1 f 1 f 0 . 8 ? 3 . 3 v 5 v ldo 33 10 ? 10 ? 0 . 1 f c 5 10 ? 1 f c 33 maxim integrated 18 MAX14826 io-link device transceiver www.maximintegrated.com
in spi mode, use the ldo33dis bit in the mode register to disable the 3.3v ldo. see the mode register [r1, r0] = [1, 1] section for more information. ldo33 cannot be disabled in parallel mode. v 5 and ldo33 are not protected against short-circuits. power-up the c/q and do driver outputs and the uv output are high impedance when v cc , v 5 , v l , and/or ldo33 volt - ages are below their respective undervoltage thresh - olds during power-up. uv goes low and the drivers are enabled when all these voltages exceed their respective undervoltage lockout thresholds. the drivers are automatically disabled if v cc , v 5 , or v l falls below its threshold. undervoltage detection the device monitors v cc , v 5 , v l , and optionally ldo33 for undervoltage conditions. the c/q and do drivers, as well as uv, are high-impedance when any monitored volt - age falls below its uvlo threshold. v cc , v 5 , and v l undervoltage detection cannot be dis - abled. when v cc falls below the v ccuvlo threshold, uv asserts high, and irq / cqoc asserts low. in spi mode, the uv24 and uv24int bits are also set. the spi register contents are unchanged while v 5 is pres - ent, regardless of the state of v cc and ldo33. the spi interface is not accessible and irq / cqoc is not available when uv is asserted due to a v 5 or v l undervoltage event. in spi mode, the internal 3.3v ldo regulator voltage (v ldo33 ) falls below the ldo33 undervoltage lockout threshold, the uv33int bit in the status register is set and irq / cqoc asserts. uv asserts if the uv33en bit in the mode register is set to 1. the uv output deasserts once the undervoltage condition is removed; however, bits in the status register and the irq / cqoc output are not cleared until the status register has been read if using spi functionality. wake-up detection (spi mode only) the device detects an io-link wake-up condition on the c/q line in push-pull, high-side (pnp), or low-side (npn) operation modes. a wake-up condition is detected when the c/q output is shorted for 80 f s (typ). wu / thsd pulses low for 190 f s (typ) when the device detects a wake-up pulse on c/q ( figure 5 ). in spi mode, set the wuinten bit in the mode register to set the wuint bit in the status register and generate an interrupt on irq / cqoc when a wake-up pulse is detect - ed. wuint is set and irq / cqoc asserts immediately after c/q is released when wuinten = 1. the wake-up dectection, wu , function is not available in parallel mode. for io-link applications, monitor the cqoc / irq output with a microcontroller to detect the short-circuit on a c/q driver during a wake-up event. short-circuit detect outputs (parallel mode only) the MAX14826 features independent overcurrent inter - rupt outputs for the c/q and do drivers. when an overcurrent condition occurs on c/q, irq/cqoc pulses low. ( figure 9 ) similarly, when an overcurrent condition occurs on do, sdo/ dooc pulses low. irq/cqoc and/or sdo/ dooc will also pulse low when driving capacitive and lamp loads. the drivers must deliver maximum current to these loads/lamps as they are being charged up or turned on. figure 9. short-circuit detect output load current 6 . 3 ms 400 ms i oh irq / cqoc or sdo / dooc v l gnd maxim integrated 19 MAX14826 io-link device transceiver www.maximintegrated.com
note that a short negative pulse on irq/cqoc and/or sdo/dooc will occur at each driver switching event, even when no loads are driven. thermal protection and considerations the internal ldos and drivers can generate more power than the package for the devices can safely dissipate. ensure that the driver ldo loading is less than the pack - age can dissipate. total power dissipation for the device is calculated using the following equation: p total = p c/q + p do + p 5 + p ldo33 + p q + p clcq + p cldi where p c/q is the power generated in the c/q driver, p do is the power dissipated by the do driver, p 5 and p ldo33 are the power generated by the ldos, p q is the quies - cent power generated by the devices. ensure that the total power dissipation is less than the limits listed in the absolute maximum ratings section. use the following to calculate the power dissipation (in mw) due to the c/q driver: p c/q = [i c/q (max)] [0.5 + 7 i c/q (max)] calculate the internal power dissipation of the do driver using the following equation: p do = [i do (max)] [0.5 + 7 i do (max)] calculate the power dissipation in the 5v ldo, v 5 , using the following equation: p 5 = (v ldoin - v 5 ) i 5 where i 5 includes the i ldo33 current sourced from ldo33. calculate the power dissipated in the 3.3v ldo, ldo33, using the following equation: p ldo33 = 1.7v i ldo33 calculate the quiescent power dissipation in the device using the following equation: p q = i cc (max) v cc (max) thermal shutdown all regulators and the c/q and do output drivers are automatically switched off when the internal die tempera - ture exceeds the +165c (typ) thermal shutdown thresh - old. the wu/thsd output asserts low during thermal shutdown and spi communication is not available. regulators are automatically switched on and wu/thsd deaaserts when the internal die temperature falls below the thermal shutdown threshold plus hysteresis. the internal registers return to their default state when the v 5 regulator is switched on. overtemperature warning (spi mode only) in spi mode, bits in the status and mode registers are set when the temperature of the device exceeds +127c (typ). the otempint bit in the status register is set and irq / cqoc asserts when the otemp bit in the mode reg - ister is set. read the status register to clear the otempint bit and irq / cqoc . the otemp bit is cleared when the die temperature falls to +104c. the device continues to operate normally unless the die temperature reaches the +165 n c thermal shutdown threshold, when the device enters thermal shutdown. maxim integrated 20 MAX14826 io-link device transceiver www.maximintegrated.com
register functionality the devices have four 8-bit-wide registers for configuration and monitoring ( table 2 ). status register [r1, r0] = [0,0] table 2. register summary register r1 r0 d7 d6 d5 d4 d3 d2 d1 d0 status 0 0 wuint dofaultint dilvl q lvl c/qfaultint uv33int uv24int otempint cqconfg 0 1 rxfilter c/q_n/p c/q_pp c/qden q rxdis dioconfg 1 0 doinv doav don/p dopp doen dobit lidis mode 1 1 rst wuinten dofault c/qfault uv24 otemp uv33en ldo33dis bit d7 d6 d5 d4 d3 d2 d1 d0 bit name wuint dofaultint dilvl q lvl c/qfaultint uv33int uv24int otempint read/write r r r r r r r r por state 0 0 x x 0 0 0 0 reset upon read yes yes no no yes yes yes yes parallel pin confguration (spi is low) x x x x x x x x x = unknown. these bits are dependent on the di logic and c/q inputs. the status register refects the logic levels of c/q and di and shows the source of interrupts that cause an irq / cqoc hardware interrupt. the irq / cqoc interrupt is asserted when an alarm condition (otemp, uv33int, uv24, c/qfault, dofault, wuint) is detected. all bits in the status register are read-only. the interrupt bits return to the default state after the status register is read. if a c/q or do fault condition persists, the associated interrupt bits are immediately set after the status register is read. bit name description d7 wulnt wake-up interrupt request. wuint is set when an io-link wake-up request pulse is detected on c/q and the wuinten bit in the mode register is set. irq / cqoc asserts when wuint is set to 1. read the status register to clear the wuint bit and deassert irq / cqoc . d6 dofaultint do fault interrupt. dofaultint interrupt bit and dofault bit (in the mode register) are set when a fault condition occurs on the do driver output. the device registers a fault condition when a short-circuit or voltage fault is detected on do (see the do fault detection section for more information). irq / cqoc asserts when dofaultint is 1. read the status register to clear the dofaultint bit and deassert irq / cqoc . d5 dilvl di logic level. the dilvl bit mirrors the current logic level at the di input. it is the inverse of the li output and is always active regardless of the state of the lidis bit (table 2). dilvl does not affect irq / cqoc . dilvl is not changed when the status register is read. r1/r0 = register address. = register not used. maxim integrated 21 MAX14826 io-link device transceiver www.maximintegrated.com
bit name description d4 q lvl c/q logic level. the q lvl bit is the inverse of the logic level at c/q. q lvl is 1 when the c/q input level is low (< 8v) and is 0 when the c/q logic level is high (> 13v) (table 3). q lvl remains active when the c/q receiver output, rx is disabled (rxdis = 1). q lvl does not affect irq / cqoc . q lvl is not changed when the status register is read. d3 c/qfaultint c/q fault interrupt. the c/qfaultint interrupt bit and c/qfault bit (in the mode register) are set when a short-circuit or voltage fault occurs on the c/q driver output (see the c/q fault detection section for more information). irq / cqoc asserts when c/qfault is 1. read the status register to clear the c/qfaultint bit and deassert irq / cqoc . d2 uv33int internal 3.3v ldo (ldo33) undervoltage warning. both the uv33int interrupt bit and the uv33en bit (in the mode register) are set when v ldo33 falls below the 2.4v ldo33 undervoltage threshold. if uv33en is set in the mode register, irq / cqoc asserts low when the uv33int bit is 1. read the status register to clear the uv33int bit and deassert irq / cqoc . set the uv33en bit to 1 in the mode register to enable undervoltage monitoring for uv33int. when enabled, uv asserts high when the uv33int bit is 1. uv deasserts when v ldo33 rises above the ldo33 undervoltage threshold. d1 uv24int v cc undervoltage interrupt. the uv24int interrupt bit and the uv24 bit (in the mode register) are set when the v cc voltage falls below the 7.4v undervoltage threshold. irq / cqoc asserts low when the uv24int bit is 1. read the status register to clear the uv24int bit and deassert irq / cqoc . v cc undervoltage detection cannot be disabled. d0 otempint overtemperature warning. the otempint interrupt bit and the otemp bit (in the mode register) are set when a high-temperature condition is detected by the devices. otemp is set when the temperature of the die exceeds +127c (typ). otempint is set and irq / cqoc asserts when the otemp bit is 1. the otempint bit is cleared and irq / cqoc deasserts when the status register is read. once cleared, otempint is not reset if the die temperature remains above the thermal warning threshold and does not fall below +104c. table 3. dilvl and li output v di (v) dilvl bit li output < 5.2 0 high > 8 1 low table 4. q lvl and rx output v c/q (v) q lvl bit rx output < 8 1 high >13 0 low maxim integrated 22 MAX14826 io-link device transceiver www.maximintegrated.com
cqconfg register [r1, r0] = [0,1] bit d7 d6 d5 d4 d3 d2 d1 d0 bit name rxfilter c/q_n/p c/q_pp c/qden q rxdis read/write r/w r/w r/w r/w r/w r/w por state 0 0 0 0 0 0 parallel pin confguration (spi/ par is low) 0 cqpp and pnp pins defne mode cqpp and pnp pins defne mode 0 0 0 = register not used. x = unknown. use the cqconfg register to control the c/q receiver and driver parameters. all bits in the cqconfg register are set to 0 at power-up. bit name description d7 rxfilter c/q and di receiver filter control. the c/q and di receivers have analog lowpass flters to reduce high-frequency noise on the receiver inputs. set the rxfilter bit to 0 to set the flter corner frequency to 500khz. set the rxfilter bit to 1 to set the flter corner frequency to 1mhz (this setting is used for high-speed com3 operation). noise flters on c/q and di are controlled simultaneously by the rxfilter bit. d6 this bit is not used. d5 c/q_n/p c/q driver npn/pnp mode. the c/q_n/p bit selects between low-side (npn) and high-side (pnp) modes when the c/q driver is confgured as an open-drain output (c/q_pp = 0). set c/q_n/p to 1 to confgure the driver for low-side (npn) operation. set c/q_n/p to 0 for high-side (pnp) operation. d4 c/q_pp c/q driver push-pull operation. set c/q_pp to 1 to enable push-pull operation on the c/q driver. the c/q output is open-drain when c/q_pp is 0. d3 c/qden c/q driver enable/disable. set the c/qden bit to 1 to enable the c/q driver. set c/qden to 0 for hardware (txen) control. see table 4. d2 q c/q driver output logic. the q bit can be used to program the c/q output driver through software. the c/q driver must be enabled and tx must be high to control the c/q driver through the q bit (figure 9). c/q has the same logic polarity as the q bit. set the q bit to 0 to control the c/q driver with tx. the c/q driver output state depends on the c/q_pp and c/q_n/p bits as shown in table 5. note that table 5 assumes that the c/q driver is enabled (txen = v l or c/qden = 1). d1 rxdis c/q receiver enable/disable. set the rxdis bit to 1 to disable the c/q receiver. the rx output is high when rxdis is 1. d0 this bit is not used. maxim integrated 23 MAX14826 io-link device transceiver www.maximintegrated.com
table 5. c/qden and txen c/q driver control c/qden txen c/q driver 0 low disabled 1 low enabled x high enabled table 6. c/q driver output state tx (see note) q c/q_pp c/q_n/p c/q configuration c/q state high 1 0 0 pnp, open-drain on, c/q is high high 0 0 0 pnp, open-drain off, c/q is high-impedance high 1 0 1 npn, open-drain off, c/q is high-impedance high 0 0 1 npn, open-drain on, c/q is low high 1 1 x push-pull high high 0 1 x push-pull low x = dont care. note: tx = v l . x = dont care. figure 10. equivalent c/q logic c/q tx q maxim integrated 24 MAX14826 io-link device transceiver www.maximintegrated.com
dioconfg register [r1, r0] = [1,0] bit d7 d6 d5 d4 d3 d2 d1 d0 bit name doinv doav don/p dopp doen dobit lidis read/write r/w r/w r/w r/w r/w r/w r/w r por state 0 0 0 0 0 0 0 0 parallel pin confguration (spi/ par is low) 0 0 dopp and pnp pins defne mode dopp and pnp pins defne mode 0 0 0 x _ = register not used. x = unknown. use the dioconfg register to control the di and do interfaces. all bits in the dioconfg register are set to 0 at power- up. bit name description d7 doinv do output polarity. set the doinv bit to 1 to invert the logic of the do output. this bit also works in conjunction with the doav (table 6). do tracks the tx input with the opposite polarity when both the doav and doinv bits are set. d6 doav do antivalent operation. set the doav bit to 1 to enable antivalent output operation on do. do tracks the tx input (and the q bit) when doav is 1 (table 6). the lo input and the dobit are ignored when the doav bit is 1. d5 don/p do driver npn/pnp operation. the don/p bit selects between low- side (npn) and high-side (pnp) modes when the do driver is confgured as an open-drain output (dopp = 0). set don/p to 1 to confgure the driver for low-side (npn) operation. set don/p to 0 for high-side (pnp) operation. d4 dopp do driver push-pull operation. set the dopp bit to 1 to confgure the do driver output for push-pull operation. do is an open-drain output when dopp is 0. d3 doen do driver enable/disable. set the doen bit to 1 to enable the do driver. the do driver is high-impedance with a weak pulldown when doen is 0. d2 dobit do driver output logic. the dobit bit can be used to program the do output driver through software. drive lo high to activate dobit programming (figure 10). the do output state is given in table 7. note that table 7 assumes that the doinv bit is 0. d1 lidis li output enable/disable. set the lidis bit to 1 to disable the li output. the li output is low when lidis is 1. d0 this bit is not used. maxim integrated 25 MAX14826 io-link device transceiver www.maximintegrated.com
table 7. doav and doinv operation doav doinv tx (note 1) lo (note 1) do (note 2) c/q (note 2) 0 0 low low high high 0 0 low high low high 0 0 high low high low 0 0 high high low low 0 1 low low low high 0 1 low high high high 0 1 high low low low 0 1 high high high low 1 0 low low low high 1 0 low high low high 1 0 high low high low 1 0 high high high low 1 1 low low high high 1 1 low high high high 1 1 high low low low 1 1 high high low low table 8. do output programmed by dobit lo dobit dopp don/p do configuration do state high 0 1 x push-pull low high 1 1 x push-pull high high 0 0 0 pnp off, do is high-impedance high 1 0 0 pnp on, do is high high 0 0 1 npn on, do is low high 1 0 1 npn off, do is high-impedance low x x x see table 6 see table 6 note 1: low is when v tx or v lo = 0v; high is when v tx or v lo = v l . note 2: low is when c/q or do < 8v; high is when c/q or do >13v. x = dont care. figure 11. equivalent do logic lo dobit do doinv maxim integrated 26 MAX14826 io-link device transceiver www.maximintegrated.com
mode register [r1, r0] = [1,1] bit d7 d6 d5 d4 d3 d2 d1 d0 bit name rst wuinten dofault c/qfault uv24 otemp uv33en ldo33dis read/write r/w r/w r r r r r r/w por state 0 0 0 0 0 0 0 0 parallel pin confguration (spi/ par is low) 0 0 dooc asserts when dofault is set cqoc asserts when c/qfault is set uv asserts when uv24 is set 0 0 0 x = unknown. use the mode register to reset the MAX14826 and manage the 3.3v ldo. the mode register has bits that represent the current status of fault conditions. when writing to the mode register, the contents of the fault indication bits (bits 2 to 5) do not change. bit name description d7 rst register reset. set rst to 1 to reset all registers to their default power-up state. then set rst to 0 for normal operation. the status register is cleared and irq / cqoc deasserts (if asserted) when rst = 1. interrupts are not generated while rst = 1. d6 wuinten wake-up interrupt enable. set wuinten to 1 to enable wake-up interrupt generation. when wuinten is set, the wuint bit in the status register is set and irq / cqoc asserts when a valid wake-up condition is detected. the c/q driver must be enabled for wake-up detection. the state of wuinten does not affect the wu / thsd output. see the wake-up detection section for more information. d5 dofault do fault status. the dofault bit is set when a short circuit or voltage fault occurs at the do driver output (see the do fault detection section for more information). the dofault and dofaultint bits are both set when a fault occurs on do. dofault is cleared when the fault is removed. d4 c/qfault c/q fault status. the c/qfault bit is set when a short circuit or voltage fault occurs at the c/q driver output (see the c/q fault detection section for more information). the c/ qfault and c/qfaultint bits are both set when a fault occurs on c/q. c/qfault is cleared when the fault is removed. d3 uv24 v cc undervoltage condition. both the uv24 and the uv24int bits are set when v cc falls below v ccuvlo . uv24 is cleared when v cc rises above the v cc threshold. v 5 must be present for spi v cc undervoltage monitoring. d2 otemp temperature warning. the otemp bit is set when a high-temperature condition occurs on the devices. both the otempint interrupt in the status register and the otemp bit are set when the junction temperature of the die rises to above +127c (typ). the otemp bit is cleared when the junction temperature falls below +104c (typ). d1 uv33en ldo33 uv enable. set the uv33en bit to 1 to assert the uv output when ldo33 voltage falls below the 2.4v (typ) undervoltage lockout threshold. the uv33en bit does not affect the uv33int bit in the status register; irq / cqoc asserts when v ldo33 falls below v ldo33uvlo regardless of the state of uv33en. d0 ldo33dis ldo33 enable/disable. set ldo33dis to 1 to disable the 3.3v linear regulator (ldo33). maxim integrated 27 MAX14826 io-link device transceiver www.maximintegrated.com
spi interface the device communicates through an spi-compatible 4-wire serial interface when spi/ par is high. the inter - face has three inputsclock (sclk/cqpp), chip select ( cs /pnp), and data in (sdi/dopp)and one data out (sdo/ dooc ). the maximum spi clock rate for the device is 12mhz. the spi interface complies with clock polarity cpol = 0 and clock phase cpha = 0 (see figure 12 and figure 13 ). the spi interface is not available when v 5 or v l are not present. figure 12. spi write cycle figure 13. spi write cycle r0 d7 d6 d5 d4 d3 d2 d1 d0 sclk/cqpp r_ = register address d_ = data bit = clock edge that initiates latching of sdi data sdi/dopp w 0 0 0 0 0 r1 cs/pnp cs/pnp sclk/cqpp sdi/dopp 0 0 0 0 0 r1 r0 r d7 d6 d5 d4 d3 d2 d1 d0 sdo/dooc x x r_ = register address d_ = data bit = clock edge that initiates latching of sdi data = clock edge that initiates writing of sdo data maxim integrated 28 MAX14826 io-link device transceiver www.maximintegrated.com
applications information transient protection inductive load-switching, surges, and bursts create high transient voltages. c/q, do, and di should be protected against high overvoltage and undervoltage transients. positive voltage transients on c/q, do, and di must be limited to +55v relative to gnd and negative voltage transients must be limited to -55v (relative to v cc ) on do and c/q and to -55v (relative to gnd) on di. figure 14 shows suitable protection using tvs diodes to meet both the iec 61000-4-2 esd and iec 61000-4-4 burst testing. other protection schemes may also be suitable. the v cc and ldoin must be protected against transients that occur during hot-plugging of the l+ sensor supply (v cc ). to protect the device, place a 10 w resistor and 1f capacitor before ldoin and connect an rc between the sensor supply into and v cc , as shown in figure 8 . ensure that the rc time constant of the filter on v cc is at least 0.8s. optional external powering the MAX14826 is powered by v cc and v 5 . v l is a reference voltage input to set the logic levels of the microcontroller interface. the logic and spi interface are operational when v 5 and v l are present even if v cc is not present. the v p output provides a reverse-polarity-protected voltage one diode drop below v cc and can be used for supplying external circuitry, like power supplies. the current drawn from v p cannot exceed 50ma. be aware that capacitance on v p can cause transient currents at power-up equal to c x dv cc /dt. v 5 is typically powered by the internal 5v regulator, but can alternatively be powered by an external 5v regula - tor. when powering v 5 externally, connect ldoin to v 5 . ( figure 15 ). this configuration disables operation of the internal 5v regulator and reduces power consumption. figure 14. MAX14826 operating circuit with tvs protection gnd c / q do v cc ldoin 1 f v p 1 uf 0 . 8 ? sdc 36 di sdc 36 max 14826 10 ? maxim integrated 29 MAX14826 io-link device transceiver www.maximintegrated.com
figure 15. using an optional external supply to power the MAX14826 1 2 4 3 10k? MAX14826 0.8? 1f sdc36 0.1f 1f v cc vp uv gpio2 ldoin do lx fb gnd spi in 5v step-down regulator en c/q l+ l- gnd di dodis gnd v 5 v cc ldo33 v l spi/ par microcontroller wu/thsd irq rx rx tx tx txen rts lo gpio1 3.3v max17552 5v maxim integrated 30 MAX14826 io-link device transceiver www.maximintegrated.com
package information for the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages . note that a +, #, or - in the package code indicates rohs status only. package drawings may show a different suffix character, but the drawing pertains to the package regardless of rohs status. package type package code outline no. land pattern no. 24 tqfn-ep t2444+4 21-0139 90-0022 ordering information part temp range pin-package MAX14826gtg+ -40c to +105c 24 tqfn-ep* + denotes a lead(pb)-free/rohs-compliant package. * ep = exposed pad. maxim integrated 31 chip information process: bicmos MAX14826 io-link device transceiver www.maximintegrated.com
revision history revision number revision date description pages changed 0 9/14 initial release ? 2014 maxim integrated products, inc. 32 maxim integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim integrated product. no circuit patent licenses are implied. maxim integrated reserves the right to change the circuitry and specifcations without notice at any time. the parametric values (min and max limits) shown in the electrical characteristics table are guaranteed. other parametric values quoted in this data sheet are provided for guidance. maxim integrated and the maxim integrated logo are trademarks of maxim integrated products, inc. MAX14826 io-link device transceiver for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxim integrateds website at www.maximintegrated.com.

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